https://llmobile.kavents.com/tags/chips/A concise news ticker covering AI on mobile devices, local models, apps and hardware.en-GBhttps://llmobile.kavents.com/ticker/mediatek-dimensity-9600-pro/https://llmobile.kavents.com/ticker/mediatek-dimensity-9600-pro/Tue, 15 Sep 2026 00:00:00 +0200MediaTek announced the Dimensity 9600 Pro, a flagship smartphone chip built on a 2nm process. According to the company, its NPU 1090 supports on-device applications with models of up to 30B parameters. MediaTek reports 51% higher LLM prefill performance, the phase where the model reads the prompt, and 55% higher token generation per watt, measured on demo devices in its own labs. The chip pairs the NPU 1090 with a second-generation Super Efficient NPU, which MediaTek says cuts power consumption for always-on AI by 40%. The platform supports LPDDR6 memory and UFS 5.0 storage. In September 2025, MediaTek announced that it had completed the tape-out, the final design handoff to the fab, of a flagship chip on TSMC’s N2P 2nm process, with volume production expected in late 2026. The CPU uses a 2+3+3 layout of eight big cores, with two C2-Ultra cores at up to 4.55 GHz. MediaTek states up to 17% higher single-core and up to 15% higher multi-core performance over the previous generation, and up to 61% lower multi-core power consumption. The first smartphones with the Dimensity 9600 Pro and the related Dimensity 9600M are expected to launch this quarter, according to MediaTek. Source: https://www.mediatek.com/press-room/mediatek-dimensity-9600-pro-sets-new-standard-for-flagship-smartphone-chips Read the article: https://llmobile.kavents.com/ticker/mediatek-dimensity-9600-pro/ChipsAndroidSmartphoneMediaTekhttps://llmobile.kavents.com/ticker/arm-create-china-2026/https://llmobile.kavents.com/ticker/arm-create-china-2026/Fri, 11 Sep 2026 00:00:00 +0200Arm has published five developer takeaways from Arm Create, its developer events in Shanghai and Shenzhen. Two of them concern on-device AI. Arm says model choice starts with the workload and not with model size alone, and that developers should decide which parts of an application stay on the device, which run on nearby edge infrastructure and which need the cloud. The Shenzhen panel included Alibaba Qwen, ModelBest, Tencent Hunyuan and Ultralytics. In the Shanghai keynote, Shantu Roy, Arm’s VP of Developer Relations, discussed the Arm AI Portal. Arm says the portal lists models validated and optimized for Arm-based platforms, together with performance data for specific targets, code and deployment workflows. Coding agents can reach the same information through the Arm MCP Server. The recap shows the portal’s evaluation of Qwen3-TTS 0.6B Custom Voice, a multilingual streaming text-to-speech model from Alibaba, on a mobile CPU. The entry lists a vivo X300 with 8 CPU cores and 16 GB of memory, SME2, the XNNPACK and KleidiAI optimizations, FP16 weights and the LiteRT runtime. It reports a real-time factor of 1.2x against a baseline of 0.28x and a median end-to-end latency of 3,878 ms against 16,877 ms. Peak memory is 4,727 MB against 6,718 MB, and the evaluation uses the English subset of the MiniMaxAI TTS-Multilingual-Test-Set. Evaluation results in the Arm AI Portal, as shown in Arm's recap. Source: Arm. Arm also points to Arm CSS for Mobile 2, which combines the Arm C2 CPU Cluster with SME2 and the Mali G2-Ultra NX GPU. Arm says the platform supports new on-device AI experiences on mobile. The next Arm Create event moves to the US, and Arm has not given a date. Source: https://newsroom.arm.com/blog/takeaways-from-arm-create-china-2026 Read the article: https://llmobile.kavents.com/ticker/arm-create-china-2026/ChipsModelsAndroidTTShttps://llmobile.kavents.com/ticker/iphone-18-pro-a20-pro-neural-engine/https://llmobile.kavents.com/ticker/iphone-18-pro-a20-pro-neural-engine/Wed, 09 Sep 2026 19:00:00 +0200Apple has introduced the iPhone 18 Pro and iPhone 18 Pro Max with the A20 Pro chip. According to Apple, the chip has a new dual 16-core Neural Engine, 32 cores in total, which the company describes as double the AI processing power of A19 Pro. Apple says the Neural Engine accelerates on-device AI models and computational photography. Image: Apple. The A20 Pro also offers 50 percent more memory bandwidth than A19 Pro, and its 6-core CPU includes integrated Neural Accelerators. Apple positions the chip for “more advanced on-device AI workloads” alongside games. The phones ship with iOS 27, Apple Intelligence and the new Siri AI. Apple states that Apple Intelligence uses on-device processing together with Private Cloud Compute. Pre-orders start on 12 September, with availability from 18 September; prices start at $1,199 for the iPhone 18 Pro and $1,299 for the iPhone 18 Pro Max, both with 256 GB. Source: https://www.apple.com/newsroom/2026/09/apple-debuts-iphone-18-pro-and-iphone-18-pro-max/ Read the article: https://llmobile.kavents.com/ticker/iphone-18-pro-a20-pro-neural-engine/AppleiPhoneChipsNPUhttps://llmobile.kavents.com/ticker/arm-mali-g2-ultra-nx/https://llmobile.kavents.com/ticker/arm-mali-g2-ultra-nx/Tue, 08 Sep 2026 00:00:00 +0200Arm has introduced the Mali G2-Ultra NX, a smartphone GPU that places dedicated neural accelerators inside each shader core. The accelerators reuse the GPU’s memory system, coherent caches and control structures, support INT8 and INT16 processing and include hardware-accelerated optical flow for motion estimation. Arm calls it the first AI-native Mali GPU and positions the accelerators for neural graphics at 1 W. The GPU is part of the Arm CSS for Mobile 2 platform. The GPU reaches up to 24% higher benchmark performance than the previous generation and 14% higher performance in non-AI gaming workloads, Arm says. Its neural graphics features are Neural Super Sampling, which reconstructs a higher-resolution image from a lower-resolution render, Neural Frame Rate Upscaling, which generates intermediate frames, and Neural Super Sampling and Denoising, which combines upscaling with denoising for ray-traced scenes. Arm says frame rate upscaling supports up to 120 FPS for longer gaming sessions. In its Neural Dawn demo, Arm reports up to 4x higher performance efficiency and up to 70% lower external memory traffic. Arm's overview slide for the Mali G2-Ultra NX. Source: Arm. Arm's diagram of how Neural Frame Rate Upscaling builds an intermediate frame. Source: Arm. The new execution engine is the largest update to the Mali instruction set architecture in seven generations, Arm says, with up to 2x more registers per warp. The third-generation hardware ray tracing unit adds support for Opacity Micromaps, which handle complex transparent geometry. Arm reports up to 13% lower DRAM traffic on ray tracing benchmarks, a 30% higher frame rate and up to 70% less ray tracing work in a scene from Moku’s Central Garden. For developers, Arm offers the Arm Neural Graphics Development Kit with machine learning extensions for Vulkan, plug-ins for Unreal Engine, an SDK for custom engines and tools for profiling, training and model optimization. Arm names integrations with Tencent Games Central Tech’s Magic Dawn engine, Unity China’s Tuanjie Engine and Unreal Engine MegaLights. Keli Zhou, engine lead for Where Winds Meet, says the game will be among the first to bring Arm Neural Technology to players. Arm’s post names no launch dates for devices with the GPU. Source: https://newsroom.arm.com/blog/arm-mali-g2-ultra-nx-ai-native-mobile-graphics Read the article: https://llmobile.kavents.com/ticker/arm-mali-g2-ultra-nx/ChipsAndroidhttps://llmobile.kavents.com/ticker/arm-css-for-mobile-2/https://llmobile.kavents.com/ticker/arm-css-for-mobile-2/Tue, 08 Sep 2026 00:00:00 +0200Arm has introduced Arm CSS for Mobile 2, a compute platform for smartphone chips that combines the C2 CPU cluster, the Mali G2-Ultra NX GPU and the SI L2 system interconnect. The C2 cluster pairs C2-Ultra and C2-Pro CPUs with two SME2 units, the Scalable Matrix Extension 2 that speeds up matrix math for AI on the CPU. Arm says this doubles the SME2 capability of the previous-generation configuration and reports up to 1.7x performance across the latest AI models. The cluster delivers up to 15% higher single-thread performance, 15% faster web browsing, 12% faster app launch and 12% higher multi-thread performance, Arm reports. For AI, it cites a peak uplift of up to 70% in selected tasks. Its slide compares speech, personal memory retrieval and prefill, the phase where a model reads the prompt, against the C1-Ultra with SME2. In a representative agentic workflow covering speech processing, memory retrieval, reasoning, app execution and web browsing, the C2-Ultra with two SME2 units finishes 24% faster than the previous generation, according to Arm. Arm's own comparison of the C2-Ultra with the C1-Ultra, with the AI tasks measured against the C1-Ultra with SME2. Source: Arm. The example flagship configuration in Arm’s slides has two C2-Ultra and six C2-Pro cores. The Mali G2-Ultra NX GPU integrates neural accelerators into its shader cores and adds a new execution engine and a third-generation ray tracing unit for neural graphics. Arm says the SI L2 interconnect provides lower-latency access, higher bandwidth, coherency and quality-of-service controls for CPU, GPU and other resources working at the same time. Partners can use each component on its own or combine them with custom and third-party IP. Arm's slide for the C2-Ultra CPU with an example flagship cluster layout. Source: Arm. On the software side, Arm lists KleidiAI, its optimized libraries for Arm CPUs including SME2 paths, plus integrations with common AI frameworks. The Arm AI Portal offers validated models with performance and accuracy data, code examples and deployment resources, and the Arm MCP Server connects them to agentic development tools. vivo says it is bringing Arm Neural Technology to its latest flagship smartphones built on the platform, aimed at mobile gaming. Arm’s post names no launch dates for devices with CSS for Mobile 2. Source: https://newsroom.arm.com/blog/arm-css-for-mobile-2-and-c2-cpu-cluster Read the article: https://llmobile.kavents.com/ticker/arm-css-for-mobile-2/ChipsAndroidhttps://llmobile.kavents.com/ticker/pixel-11-tensor-g6/https://llmobile.kavents.com/ticker/pixel-11-tensor-g6/Wed, 12 Aug 2026 19:00:00 +0200Google has announced the Pixel 11, Pixel 11 Pro and Pixel 11 Pro XL, built around the Tensor G6 chip. Google states that Tensor G6 packs 50 percent more TPU compute and, paired with the latest Gemini Nano model, processes on-device AI tasks up to 3.5 times faster while using up to 3.5 times less energy. The company also cites an upgraded CPU with 25 percent faster web browsing and 15 percent quicker app launches, and says the chip powers the 30x Super Zoom on the 5x telephoto lens. Google does not publish RAM figures, model sizes or per-task latency in the announcement. Pre-orders opened on 12 August, with retail availability from 20 August. ▶Meet Google Pixel 11 ProLoading connects your browser to www.youtube-nocookie.com, which may process your IP address and use cookies. Load contentOpen externallyVideo: Made by Google. Source: https://blog.google/products-and-platforms/devices/pixel/google-pixel-11-pro-xl/ Read the article: https://llmobile.kavents.com/ticker/pixel-11-tensor-g6/GooglePixelChipsNPUGemini Nanohttps://llmobile.kavents.com/ticker/a19-pro-neural-accelerators/https://llmobile.kavents.com/ticker/a19-pro-neural-accelerators/Tue, 09 Sep 2025 20:00:00 +0200Apple announced the A19 Pro alongside the iPhone 17 Pro on September 9, 2025. Its 6-core GPU carries Neural Accelerators built into each core, which Apple says work together with the 16-core Neural Engine to power AI models, graphics and games. The company states that the chip enables running large local language models on the phone. The A19 Pro also has a 6-core CPU that Apple calls the fastest in any smartphone, along with a larger cache and more memory than the A18 Pro. Combined with a vapor chamber cooling system, Apple puts sustained performance at up to 40 percent above the previous generation. Image: Apple. The vapor chamber Apple credits for the sustained performance gain. Source: https://www.apple.com/newsroom/2025/09/apple-unveils-iphone-17-pro-and-iphone-17-pro-max/ Read the article: https://llmobile.kavents.com/ticker/a19-pro-neural-accelerators/AppleiPhoneChipsApple SiliconNPUhttps://llmobile.kavents.com/ticker/roma-qlora-accelerator/https://llmobile.kavents.com/ticker/roma-qlora-accelerator/Mon, 17 Mar 2025 10:44:00 +0100Researchers at Shanghai Jiao Tong University, Peking University and Microsoft Research Asia described ROMA on March 17, 2025, an accelerator design that holds a quantised language model in on-chip read-only memory. The paper reports results from Verilog synthesis against TSMC’s 7 nm standard cell library, not from a fabricated chip and not from an FPGA prototype, so every speed, area and power figure in it is a toolchain estimate rather than a measurement on hardware. On that basis the authors report peak decoding of 31,800 tok/s for a 4-bit 3B Llama model with an empty KV cache. The design splits storage by how often the weights change. The frozen base model, quantised to 2-bit or 4-bit, sits in ROM, which cannot be rewritten once the chip has been manufactured, while the small trainable LoRA adapter and the KV cache sit in SRAM, which can. The authors argue that a base model is stable enough for that, with updates expected over years rather than months, and that adaptation to new tasks happens in the adapter instead. What ROM buys is density, and the paper puts a ROM bit cell at roughly a third of the area of an SRAM bit cell in TSMC’s 7 nm memory compiler, enough to fit the whole quantised model on chip without external memory. The synthesised configuration carries 1.86 GB of ROM and 304 MB of SRAM at 500 MHz, with an area of 503.7 mm² and power of 33.1 W, the area and latency coming from Synopsys Design Compiler and the power from Synopsys PrimeTime PX. It holds either a 4-bit 3B or a 2-bit 8B Llama model entirely on chip, and for the 3B model with a rank-16 adapter the authors report a time to first token of 5.6 ms at 256 input tokens and 140.2 ms at 4K, with decoding staying above 10,000 tok/s once 4K tokens are cached. They also compare against measured hardware, an Intel i5-1135G7 running llama.cpp at 6.8 tok/s and an Nvidia RTX 4090 running TensorRT-LLM at 219 tok/s on the same 4-bit 3B model, against 20,078 tok/s for the ROMA estimate at a 256-token input. Most of the paper’s engineering goes into shrinking the ROM. A structure the authors call B-ROM stores the constant bits in the chip’s wiring instead of in transistors, which cuts the transistor count to about a quarter and the ROM area by around 40 percent against a standard ROM, and a fused cell layout places that wiring-heavy structure in the same physical area as the transistor-heavy compute logic. The paper states no tapeout, no fabrication schedule and no cost figures, and it names the fixed base model as the price of the approach, since ROM content is set at manufacture. It is posted under the arXiv perpetual non-exclusive license. Source: https://arxiv.org/abs/2503.12988 Read the article: https://llmobile.kavents.com/ticker/roma-qlora-accelerator/ChipsMemoryQuantisationResearchLlamahttps://llmobile.kavents.com/ticker/genai-at-the-edge-survey/https://llmobile.kavents.com/ticker/genai-at-the-edge-survey/Wed, 19 Feb 2025 21:43:00 +0100Seven researchers at Johns Hopkins University and Duke University published a survey of generative AI on edge devices on February 19, 2025. Most of the accelerator hardware it collects has not been built. Its table of 12 accelerators for language and diffusion models covers 8 simulator studies against 4 fabricated chips, and the highest peak energy efficiency in it is 74.34 TOPS/W, from a 28nm computing-in-memory chip designed for Stable Diffusion. Compression is the part the survey treats as settled enough to quantify, and it attributes every figure to the work it reviews. It reports unstructured pruning reaching up to 60 percent sparsity on large models and a sparsity-aware inference system turning that into a 3 times speedup, while structured pruning that removes whole components gives about 2 times with little quality loss. Quantisation has been taken to 1 bit per weight in work such as BitNet, and the survey names what is still open there as holding generation quality under extreme compression and finding efficient ways to train quantised models on the edge devices themselves rather than only to run them. The frameworks chapter is where the survey names hardware a reader can buy. It cites a measurement that applying NVIDIA’s TensorRT to transformer models on a Jetson Xavier cuts latency by over 60 percent with negligible accuracy loss, and points to MELTing Point, a benchmark suite that tracks language model energy use and memory footprint across smartphones and Jetson boards. The authors state that no dedicated survey of generative AI at the edge existed before theirs, close by naming model personalisation and security across distributed edge nodes as the challenges that persist, and publish on arXiv under a Creative Commons Attribution 4.0 license. Diagram: Navardi and colleagues, from the survey. Source: https://arxiv.org/abs/2502.15816 Read the article: https://llmobile.kavents.com/ticker/genai-at-the-edge-survey/ResearchChipsQuantisationNPUhttps://llmobile.kavents.com/ticker/bitnet-b1-58/https://llmobile.kavents.com/ticker/bitnet-b1-58/Tue, 27 Feb 2024 19:56:00 +0100Microsoft Research and the University of Chinese Academy of Sciences published BitNet b1.58 on February 27, 2024, a language model in which every single weight is one of three values, -1, 0 or 1. At 3B parameters the authors measure it at 2.22 GB of memory against 7.89 GB for a full-precision Llama-style model of the same size trained on the same number of tokens, a 3.55 times reduction, with a slightly lower perplexity of 9.91 against 10.04. Three possible values need log2(3) bits to store, which is roughly 1.58 and where the name comes from. What that buys is a change to the matrix multiplication that dominates the work of running a model. A normal model multiplies each weight by an activation in floating point and sums the products, but multiplying by -1, 0 or 1 is only a sign flip, a skip or a copy, so the paper states that the matrix multiplication of BitNet “only involves integer addition”. Activations stay at 8 bits. The models are trained from scratch at this precision rather than trained in full precision and squeezed down afterwards, which is how most low-bit models on phones are produced today. The authors trained BitNet b1.58 and their own reproduced Llama baseline on the same data for the same number of tokens at each size, and compare the two directly. They report that BitNet b1.58 starts to match the full-precision baseline in perplexity at 3B and on zero-shot end tasks from 3B as well, where it averages 50.2 against 49.7. The efficiency figures widen with size. Memory drops 2.60 times at 700M, 2.93 times at 1.3B and 3.55 times at 3B, and latency per output token falls 1.23 times, 1.67 times and 2.71 times across the same three sizes. For throughput the authors ran 70B models on two A100 cards and report a batch size of 176 against 16 and 2977 tokens per second against 333, an 8.9 times gain. They also calculate that on 7nm chips the arithmetic for matrix multiplication costs 71.4 times less energy, because integer addition is far cheaper than floating-point multiply-accumulate. The paper names no model release and its arXiv listing marks it as work in progress. The authors argue the approach suits CPUs, “which are the main processors used in edge and mobile devices”, and say the lower memory and energy cost is what would let such models run there. They close by calling for new hardware and systems designed specifically for 1-bit models. Update, April 16, 2025. Microsoft released BitNet b1.58 2B4T, a 2B model trained from scratch on 4 trillion tokens at ternary precision, which the team calls the first open-source native 1-bit model at that scale. The report puts its non-embedding memory at 0.4 GB against 1.4 GB for Gemma-3 1B and 2.6 GB for Qwen2.5 1.5B, measures CPU decoding at 29 ms per token on a 13th Gen Intel Core i7-13800H using 8 threads against 41 ms and 65 ms for the same two models, and estimates energy at 0.028 J against 0.186 J and 0.347 J. Across the benchmark suite it averages 54.19, above Llama 3.2 1B at 44.90 and just under Qwen2.5 1.5B at 55.23. The weights are on Hugging Face, with a custom CUDA kernel for GPUs and CPU inference through bitnet.cpp, the runtime Microsoft published in October 2024 and measured at 2.37 to 6.17 times faster than the baseline on x86 CPUs and 1.37 to 5.07 times faster on ARM. Source: https://arxiv.org/abs/2402.17764 Read the article: https://llmobile.kavents.com/ticker/bitnet-b1-58/MicrosoftResearchQuantisationMemoryChipshttps://llmobile.kavents.com/ticker/snapdragon-8-gen-3/https://llmobile.kavents.com/ticker/snapdragon-8-gen-3/Tue, 24 Oct 2023 19:00:00 +0200Qualcomm launched the Snapdragon 8 Gen 3 at its Snapdragon Summit in Hawaii on October 24, 2023, calling it its first mobile platform designed with generative AI in mind. On the product page the company states support for generative models with up to 10 billion parameters on device and up to 20 tokens per second for large language models. Qualcomm puts the Hexagon NPU at 98 percent faster than the previous generation and claims 40 percent better performance per watt for sustained AI inference. It lists the Kryo CPU at 30 percent more performance and 20 percent better power efficiency, and the Adreno GPU at 25 percent faster rendering with 25 percent better efficiency. Among the workloads Qualcomm names for local execution are Stable Diffusion, virtual assistants and chatbots. Devices were announced by ASUS, Honor, iQOO, MEIZU, Nubia, OnePlus, OPPO, realme, Redmi, RedMagic, Sony, vivo, Xiaomi and ZTE. Image: Qualcomm. Source: https://www.qualcomm.com/news/releases/2023/10/qualcomm-launches-premium-snapdragon-8-gen-3-to-bring-generative Read the article: https://llmobile.kavents.com/ticker/snapdragon-8-gen-3/QualcommChipsNPUAndroid